The invention relates generally to semiconductor device fabrication and, in particular, to transistors, device structures incorporating transistors, methods of fabricating transistors, and design structures for a transistor.
Integrated circuits may include multiple field effect transistors fabricated using a bulk wafer of semiconductor material or the device layer of a semiconductor-on-insulator (SOI) wafer. Field effect transistors of planar device architecture have source region and drain regions defined in the semiconductor material of the bulk wafer of the device layer of the SOI wafer. The source and drain regions are separated by a channel region of opposite conductivity type. Charge carriers flow across the channel region under control of a voltage applied to a gate electrode. Complementary Metal Oxide Semiconductor (CMOS) technology, which is the prevailing technology used in integrated circuit fabrication, integrates two distinct varieties of field effect transistors known as “n-channel” and “p-channel”. Electron transport is responsible for carrier flow and output current in n-channel MOS field effect transistors. Hole transport is responsible for carrier flow and output current in p-channel MOS field effect transistors.
Improved transistor device structures, improved methods for fabricating transistors, and improved transistor design structures are needed.